Ferroelectric random access memory (FRAM) is a non-volatile memory which stores data by using two different polarization orientations of a ferroelectric domain (or referred to as “electric domain”) in an electric field as logic information (“0” or “1”), and can be also referred to as “ferroelectric memory”.
The storage medium layer of a ferroelectric memory is a ferroelectric thin film layer having a reversible (or “switchable”) ferroelectric domain. Currently, the fastest speed of reversing an electric domain that can be measured in a lab can reach up to 0.2 ns. In fact, it can be even faster. Usually, the reversing speed of electric domain determines the read-write time of the memory, a coercive voltage for electric domain reversing determines the read-write voltage of elements, and it will decrease almost in equal proportion to a reduction of the thickness of the thin film. Therefore, the ferroelectric memory has such advantages as fast speed of data reading, low drive voltage, high density of storage, etc., and has earned widespread attention and rapid development in recent years.
Currently, the ferroelectric memory can be mainly divided into two categories according to a basic mode of work or operation: a destructive readout (DRO) FRAM and a non-destructive readout (NDRO) FeFET.
The DRO FRAM uses a ferroelectric capacitor (which is a capacitor formed by using a ferroelectric thin film layer as the medium layer) to replace the conventional charge-storing capacitor, and uses a polarization reversal thereof to realize writing and reading of data. So far, all the ferroelectric memories applied in the market adopt this mode of operation, wherein one transistor T and one ferroelectric capacitor C (i.e., 1T1C) constitutes a storage unit, and the 1T1C storage unit serves as the basis for circuit design. During the read operation, a charge integrating method is used, wherein whether the electric domain of the ferroelectric thin film layer is reversed is determined by reading a voltage of a reference capacitor connected in series with the 1T1C storage unit, thus recognizing the logic information in the storage unit. In the read operation of such ferroelectric memory, the reading of voltage will lead to a reversal of electric domain of the ferroelectric thin film layer. Therefore, it has disadvantages that the reading of information is destructive, the liability is low, and the original logic information status has to be written back again after the reading operation. In addition, with the improvement of integration density of elements, the area of ferroelectric capacitor C of the storage unit is continuously decreasing, whereas the readout charge is in direct proportion to the area of ferroelectric capacitor C, and thus the charge that can be read out is also becoming less and less; when the size of the storage unit of elements is smaller than 260 nm, the current readout circuit substantially cannot recognize the logic information stored in the storage unit, thus severely hindering the development of ferroelectric memory towards a high density trend.
The non-destructive readout (NDRO) ferroelectric memory is a ferroelectric field effect transistor (FeFET) in which a MFS structure is formed by using a ferroelectric thin film layer to replace the gate medium layer of a conventional MOSFET. The magnitude of source-drain current Ids can be varied under a control over the polarization direction, the difference can reach up to several orders of magnitude, and a non-destructive reading of the stored information can be realized with a very small voltage. The NDRO ferroelectric memory has such characteristics as high density integration, high reading and writing speed, non-destructive accessing, low power consumption, etc. However, since the retention performance of logic information of this device is poor and typically reaches merely several days or several months, whereas the storage market usually demands a period of no less than 10 years. Therefore, this structure is currently still in the stage of lab research, and can not be practically applied to a memory product.
Therefore, the current commercially applied DRO ferroelectric memories are mainly read out in a way of charge integrating for a ferroelectric capacitance. As summarized above, it has a disadvantage of destructive readout, and data has to be re-written after readout, thus resulting in a plenty of erasing and re-writing operations, which will cause a reduction in reliability of devices and affect reading speed of data; moreover, such a reading principle restricts a scaling-down of the ferroelectric capacitance C, and has a low storage density. For example, the current commercially applied ferroelectric memories have only 8 MB at most.